In early integrated circuit memory systems, the detailed operation of the memory system was controlled directly by a processor unit which utilized the memory. This was referred to as external control of the memory system operations because the control means was external to the memory itself. Since the operation of many memory systems requires a substantial amount of processor overhead, and since different manufacturers require different operations for optimizing their particular memories, many such systems now include an internal state machine (ISM) for controlling the operation of the memory system. The internal state machine controls the execution of the primary operations of the memory system, including reading, programming and erasing of the memory cells. Each of these primary operations is comprised of a large number of sub-operations which are necessary to carry out the primary operations, with these sub-operations also being controlled by the state machine.
FIG. 1 is a functional block diagram of a conventional non-volatile memory system 1. The core of memory system 1 is an array 12 of memory cells. The individual cells in array 12 (not shown) are arranged in rows and columns, with there being, for example, a total of 256K eight bit words stored in array 12. The individual memory cells are accessed by using an eighteen bit address A0-A17, which is input by means of address pins 13. Nine of the eighteen address bits are used by X decoder 14 to select the row of array 12 in which a desired memory cell is located and the remaining nine bits are used by Y decoder 16 to select the column of array 12 in which the desired cell is located. Sense amplifiers 50 are used to read the data contained in a memory cell during a read operation or during a data verification step in which the state of a cell is determined after a programming, pre-programming, or erase operation. The sense amplifier circuitry can be combined with the data compare and verify circuits used to compare the state of a cell to a desired state or to the input data used in programming the cell.
Programming or erasing of the memory cells in array 12 is carried out by applying the appropriate voltages to the source, drain, and control gate of a cell for an appropriate time period. This causes electrons to tunnel or be injected from a channel region to a floating gate. The amount of charge residing on the floating gate determines the voltage required on the control gate in order to cause the device to conduct current between the source and drain regions. This is termed the threshold voltage, V.sub.th, of the cell. Conduction represents an "on" or erased state of the device and corresponds to a logic value of one. An "off" or programmed state is one in which current is not conducted between the source and drain regions and corresponds to a logic value of zero. By setting the threshold voltage of the cell to an appropriate value, the cell can be made to either conduct or not conduct current for a given set of applied voltages. Thus, by determining whether a cell conducts current at a given set of applied voltages, the state of the cell (programmed or erased) can be found.
Memory system 1 contains internal state machine (ISM) 20 which controls the data processing operations and sub-operations performed on memory array 12. These include the steps necessary for carrying out programming, reading and erasing operations on the memory cells of array 12. In addition, internal state machine 20 controls operations such as reading or clearing status register 26, identifying memory system 1 in response to an identification command, and suspending an erase operation. State machine 20 functions to reduce the overhead required of an external processor (not depicted) typically used in conjunction with memory system 1.
For example, if memory cell array 12 is to be erased (typically, all or large blocks of cells are erased at the same time), the external processor causes the output enable pin OE to be inactive (high), and the chip enable CE and write enable WE pins to be active (low). The processor then issues an 8 bit command 20H (0010 0000) on data I/O pins 15 (DQ0-DQ7), typically called an Erase Setup command. This is followed by the issuance of a second eight bit command D0H (1101 0000), typically called an Erase Confirm command. Two separate commands are used to initiate the erase operation in order to minimize the possibility of inadvertently beginning an erase procedure.
The commands issued on I/O pins 15 are transferred to data input buffer 22 and then to command execution logic unit 24. Command execution logic unit 24 receives and interprets the commands used to instruct state machine 20 to initiate and control the steps required for erasing array 12 or carrying out another desired operation. If a programming operation is being executed, the data to be programmed into the memory cells is input using I/O pins 15, transferred to input buffer 22, and then placed in input data latch 30. The data in latch 30 is then made available to sense amplifier circuitry 50 for the cell programming and data verification operations. Once a desired operation sequence is completed, state machine 20 updates 8 bit status register 26. The contents of status register 26 is transferred to data output buffer 28, which makes the contents available on data I/O pins 15 of memory system 1. Status register 26 permits the external processor to monitor certain aspects of the status of state machine 20 during memory array write and erase operations. The external processor periodically polls data I/O pins 15 to read the contents of status register 26 in order to determine whether an erase sequence (or other operation) has been completed and whether the operation was successful.
Memory system 1 verifies the status of the memory cells after performing programming or erasing operations on the cells. Verification occurs by accessing each memory element and evaluating the margins (the voltage differential between the threshold voltage of the memory cells and ground level) that the element has after the operation. The system then decides whether the element needs to be reprogrammed or erased further to achieve a desired operational margin.
The memory array needs to be programmed first in a pre-programming cycle before it can be erased. This is to avoid over-erasing the bits in some memory elements to a negative threshold voltage, thereby rendering the memory inoperative. During this cycle of pre-programming, the memory system needs to check to see if the bits are programmed to a sufficient threshold voltage level. This is accomplished by a pre-programming verification cycle that uses a different evaluation procedure than a regular read operation would use. After successful completion of the pre-programming cycle, a high voltage erase operation is executed. After the erase operation is completed, some memory systems go through an operation to tighten the distribution (reduce the variance) of memory element threshold voltages. This makes the manufacturing process easier and more reproducible. After this procedure, the memory system may perform a re-verify operation to determine if the data in the memory array has remained undisturbed.
FIG. 2 is a state diagram showing the process flow (sub-operations) of a memory system of the type shown in FIG. 1 during the pre-programming, high voltage erase, and distribution adjustment cycles of a complete erase operation. The complete erase operation starts with a pre-program cycle 200. This sub-operation programs all the elements in the memory array to a logic zero value to make sure that the erase process starts from a known cell threshold voltage level. This part of the complete erase operation is used to reduce the possibility of over erasure of some of the memory elements during the later steps of the complete erase operation.
The pre-program cycle begins with an operation which increments the address of the memory cell which is to be pre-programmed 202. This is done because the pre-programming operation is executed on a cell by cell basis. This step is followed by a high voltage level set-up stage 204 which prepares the system for application of the high voltage levels (typically about 12 volts is applied to the gate of each memory cell and 5 volts to the drain) used for programming or erasing a cell. The high voltage level used for writing to (programming) the cell is then applied at stage 206.
The appropriate voltage levels for executing the data verification sequence (reading the data programmed in the cell and comparing it to a desired value) are applied to the appropriate circuitry at stage 208. This is followed by a program verification stage 210 which verifies that the programmed cell has a sufficient threshold voltage margin. This is typically accomplished by comparing the threshold voltage of the cell to a reference cell having a desired threshold voltage (corresponding to a logic value of zero). If the verification operation was not successful, steps 204, 206, 208, and 210 are repeated. Once the verification stage for a particular memory cell is successfully completed, it is followed by a program clean up stage 212.
Program clean up stage 212 conditions all internal nodes of the memory array to default values in order to prepare the memory system for the next operation. This concludes the pre-programming cycle for a given memory cell. The address of the cell to be operated on is then incremented at stage 202 and the process repeats itself until the last cell in a memory block to be erased is successfully pre-programmed. At this time, the incremented address will point to the first address location in the block, which is the first address for the next operation. When this occurs, all of the memory cells have been pre-programmed and control is passed to the high voltage erase cycle 220.
In the high voltage erase cycle, the memory system performs a block erase operation on all of the cells contained in a block of memory. The first stage in the cycle is a high voltage level set-up stage 222 which prepares the memory block for application of the high voltage pulse(es) used for erasing the cells. This is followed by a high voltage stage 224 in which a short duration, high voltage pulse is applied to erase all of the memory cells in the block of cells. This is followed by a set-up verify stage 226 which applies the appropriate voltage levels for the data verification stage to the corresponding circuits. The next stage is an erase verify stage 228 which verifies that the erase operation was successfully carried out on each cell in the block. This is accomplished by accessing the cells, address by address, and comparing the threshold voltage of the cell to a reference cell having a desired threshold voltage level (corresponding to a logic value of one).
If the erase operation was not successfully carried out (a cell was not erased to the threshold voltage margin corresponding to the desired logic value), control is passed back to the high voltage level set-up stage 222 and the high voltage cycle is carried out again to erase the entire block of cells. If the erase operation was successful for the cell under consideration, the address of the memory cell is incremented 230 and the next cell is tested for verification of the erase operation. Thus, if the maximum address of the cells in the block of memory has not been reached, erase verify stage 228 is carried out on the next memory cell in the block. If the maximum address for cells in the block has been reached (meaning that all the cells in the memory block have been successfully erased), control is passed to the distribution adjustment cycle 240.
The distribution adjustment sub-operation 240 is used to tighten the distribution (reduce the variance) of the threshold voltages of the erased memory elements. This is done by applying high voltages (i.e., 12 volts) to the gates of all the memory cells in the memory block, with the memory cell drains floating and the sources at ground potential.
The distribution adjustment cycle begins with a high voltage set-up stage 242, which is followed by a high voltage stage 244 in which the voltages used to perform the adjustment sub-operation are applied. This is followed by set-up verification 246 stage which applies the appropriate voltage levels to the corresponding circuits, and erase verification 248 stage which acts to insure that all of the erased cells are still in an erased state. If the erase verification procedure fails, a final erase 249 stage may be executed. In the final erase stage, a short erase pulse is applied to the cells in the block. After completion of the previous steps, the memory elements are checked to determine if they still contain the appropriate data. At this point the erase operation is completed.
A programming operation is carried out by following a set of steps similar to those followed in pre-program cycle 200 of FIG. 2. In particular, stages 204 through 212 of FIG. 2 describe the primary functions carried out in a regular programming operation. As a program operation is typically carried out on a specific memory cell, the increment address state 202 used in the pre-program cycle to facilitate pre-programming of every cell in the memory array is not accessed. Another difference between the programming and pre-programming operations is that in a programming operation, program verify state 210 is designed to read the data programmed into the cell and compare it to data obtained from input data latch 30, rather than to a logic value of zero, as in the pre-programming operation.
As is evident form the preceding description, the erase operation requires the use of a complex state machine. In order to reduce the time it takes to test a memory system and hence the cost of testing, it is desirable to test multiple memory systems in parallel. It is also desirable to identify faulty memory cells without having to exercise all of the features of the state machine. This aids in reducing the time it takes to test the memory system.
The integrity of the memory cells contained in an array is typically tested by programming each cell (writing data to the cells) using a prescribed test pattern and then verifying that the data was properly written. Several test patterns are used to fully check the integrity of the cells. These include, among others, a pattern of all zeros, all ones, a checkerboard pattern, and an inverse checkerboard pattern. The pattern consisting of all ones is automatically generated as a result of a regular complete erase operation. However, for the other patterns a test engineer typically issues the address of a byte to which the pattern is to be written, prescribes the test pattern data, checks the status of the memory cells to determine if the programming operation was successfully completed, and then issues the next address for the pattern writing operation. This continues until all of the memory cells in the array have been tested with the pattern. After that, another pattern may be used to further check the memory cells.
As noted, in order to reduce the cost of testing memory devices, multiple memory arrays are tested in parallel. This further slows the testing process because for each byte of the multiple arrays being tested, the test engineer has to wait for the slowest of all the devices being tested to complete the pattern writing and verification steps before the next set of bytes can be tested. After one test pattern has been successfully written to each byte of the multiple arrays, a new test pattern can be written to the memory cells in the arrays. As is apparent, manual control of this testing process by the test engineer is very time consuming, even when multiple arrays are tested in parallel.
What is desired is an apparatus for efficiently testing multiple memory devices in parallel by automatically writing each of a set of test pattern data to the memory cells in each array, and then verifying successful completion of the write operation.